In through silicon stacking (TSS), silicon chips are stacked to form 3-D electronic devices. In such devices, interconnects between the chips are constructed. These interconnects often include through silicon vias (TSVs).
Each circuit on each of the stacked chips requires ESD protection on the circuit's I/O ports. Unfortunately, ESD protection circuitry has a relatively large footprint on the silicon. When existing circuitry is split among multiple chips of a 3-D device, the circuits (and their respective ESD protection) may be separated. Consequently, ESD protection is provided on each chip to protect each portion of the circuit split amongst different chips. As a result, the ESD protection circuitry requires even more space on the 3-D stacked chips.